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| 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 01.mm -- 27 March 2006 Preliminary data sheet 1. General description The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C Class 3A. Exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 A (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger s Multiple package options s Specified from -40 C to +85 C and -40 C to +125 C 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 3 ns. Symbol Parameter Conditions CL = 5 pF; RL = 1 M; VCC = 0.8 V CL = 5 pF; RL = 1 M; VCC = 1.1 V to 1.3 V CL = 5 pF; RL = 1 M; VCC = 1.4 V to 1.6 V CL = 5 pF; RL = 1 M; VCC = 1.65 V to 1.95 V CL = 5 pF; RL = 1 M; VCC = 2.3 V to 2.7 V CL = 5 pF; RL = 1 M; VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q CL = 5 pF; RL = 1 M; VCC = 0.8 V CL = 5 pF; RL = 1 M; VCC = 1.1 V to 1.3 V CL = 5 pF; RL = 1 M; VCC = 1.4 V to 1.6 V CL = 5 pF; RL = 1 M; VCC = 1.65 V to 1.95 V CL = 5 pF; RL = 1 M; VCC = 2.3 V to 2.7 V CL = 5 pF; RL = 1 M; VCC = 3.0 V to 3.6 V fmax CI CPD maximum input clock VCC = 3.0 V to 3.6 V; frequency CL = 30 pF input capacitance power dissipation capacitance VCC = 1.8 V; f = 1 MHz VCC = 3.3 V; f = 1 MHz [1] [2] [1] [2] Min 2.4 2.0 1.6 1.3 1.2 2.4 2.3 1.8 1.8 1.6 190 - Typ 21.1 5.9 4.1 3.3 2.5 2.1 17.4 5.2 3.8 3.1 2.6 2.4 300 1.5 2.0 2.7 Max 11.7 6.8 5.4 3.6 2.9 9.7 4.9 4.9 3.6 3.1 - Unit ns ns ns ns ns ns ns ns ns ns ns ns MHz pF pF pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q [1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC. [2] 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 2 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 4. Ordering information Table 2: Ordering information Package Temperature range Name 74AUP1G175GW 74AUP1G175GM 74AUP1G175GF -40 C to +125 C -40 C to +125 C -40 C to +125 C SC-88 XSON6 XSON6 Description plastic surface mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 x 1.45 x 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 x 1 x 0.5 mm 5. Marking Table 3: Marking Marking code aT aT aT Type number 74AUP1G175GW 74AUP1G175GM 74AUP1G175GF 6. Functional diagram 6 3 MR D FF Q 4 CP 001aaa468 1 3 6 C1 1D R 001aaa469 4 1 Fig 1. Logic symbol Fig 2. IEC logic symbol CP C C C C Q C D C MR C C C C 001aaa466 Fig 3. Logic diagram 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 3 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 7. Pinning information 7.1 Pinning 74AUP1G175 74AUP1G175 CP CP 1 6 MR GND GND 2 5 VCC D D 3 001aaa467 1 6 MR 2 5 VCC 3 4 Q 4 Q 001aab657 Transparent top view Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) 74AUP1G175 CP GND D 1 2 3 6 5 4 MR VCC Q 001aae246 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) 7.2 Pin description Table 4: Symbol CP GND D Q VCC MR Pin description Pin 1 2 3 4 5 6 Description clock input (LOW-to-HIGH, edge-triggered) ground (0 V) data input flip-flop output supply voltage master reset input (active LOW) 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 4 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 8. Functional description 8.1 Function table Table 5: Function table [1] Input MR Reset (clear) Load `1' Load `0' [1] Operating mode Output CP X D X h l Q L H L L H H H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; = LOW-to-HIGH CP transition; X = don't care. 9. Limiting values Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current quiescent supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min -0.5 -0.5 [1] Max +4.6 -50 +4.6 -50 +4.6 20 +50 -50 +150 250 Unit V mA V mA V mA mA mA C mW VO < 0 V active mode and Power-down mode VO = 0 V to VCC -0.5 -65 Tamb = -40 C to +125 C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 5 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 10. Recommended operating conditions Table 7: Symbol VCC VI VO Tamb t/V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 -40 0 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V C ns/V 11. Static characteristics Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C VIH HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VCC - 0.1 1.11 1.32 2.05 1.9 2.72 2.6 V V V V V V V V 0.75 x VCC 0.70 x VCC 0.65 x VCC 1.6 2.0 V V V V Conditions Min Typ Max Unit 0.30 x VCC V 0.35 x VCC V 0.7 0.9 V V 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 6 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-state output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC CI CO VIH input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ 0.8 1.7 Max 0.1 0.3 x VCC 0.31 0.31 0.31 0.44 0.31 0.44 0.1 0.2 0.2 0.5 40 - Unit V V V V V V V V A A A A A pF pF V V V V additional quiescent supply VI = VCC - 0.6 V; IO = 0 A; current VCC = 3.3 V input capacitance output capacitance HIGH-state input voltage VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = -40 C to +85 C 0.70 x VCC 0.65 x VCC 1.6 2.0 VCC - 0.1 0.7 x VCC 1.03 1.30 1.97 1.85 2.67 2.55 - VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.30 x VCC V 0.35 x VCC V 0.7 0.9 V V V V V V V V V V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 7 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-state output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ - Max 0.1 0.3 x VCC 0.37 0.35 0.33 0.45 0.33 0.45 0.5 0.5 0.6 0.9 50 Unit V V V V V V V V A A A A A additional quiescent supply VI = VCC - 0.6 V; IO = 0 A; current VCC = 3.3 V HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = -40 C to +125 C VIH 0.75 x VCC 0.70 x VCC 1.6 2.0 V V V V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.25 x VCC V 0.30 x VCC V 0.7 0.9 V V V V V V V V V V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VCC - 0.11 0.6 x VCC 0.93 1.17 1.77 1.67 2.40 2.30 - 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 8 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-state output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ - Max 0.11 0.41 0.39 0.36 0.50 0.36 0.50 0.75 0.75 0.75 1.4 75 Unit V V V V V V V A A A A A 0.33 x VCC V additional quiescent supply VI = VCC - 0.6 V; IO = 0 A; current VCC = 3.3 V [1] One input at VCC - 0.6 V, other input at VCC or GND. 12. Dynamic characteristics Table 9: Dynamic characteristics GND = 0 V; see Figure 9 Symbol tPHL, tPLH Parameter HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q Conditions see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.4 2.3 1.8 1.8 1.6 17.4 5.2 3.8 3.1 2.6 2.4 9.7 4.9 4.9 3.6 3.1 ns ns ns ns ns ns 2.4 2.0 1.6 1.3 1.2 21.1 5.9 4.1 3.3 2.5 2.1 11.7 6.8 5.4 3.6 2.9 ns ns ns ns ns ns Min Typ [1] Max Unit Tamb = 25 C; CL = 5 pF 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 9 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 9: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol fmax Parameter maximum input clock frequency CP Conditions see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 C; CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum input clock frequency CP see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 50 190 320 420 485 550 MHz MHz MHz MHz MHz MHz 2.6 2.5 2.5 2.1 2.0 21.0 6.2 4.4 3.7 3.2 3.0 11.5 5.9 5.7 4.3 3.9 ns ns ns ns ns ns 2.6 2.3 2.1 1.7 1.6 24.7 6.8 4.8 3.9 3.0 2.7 13.3 7.9 6.1 4.3 3.6 ns ns ns ns ns ns 50 200 345 435 550 615 MHz MHz MHz MHz MHz MHz Min Typ [1] Max Unit 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 10 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 9: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol tPHL, tPLH Parameter HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q Conditions see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum input clock frequency CP see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 C; CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 3.9 3.9 3.6 3.5 3.3 35.1 9.3 6.6 5.6 4.8 4.6 18.0 8.7 8.6 6.4 5.7 ns ns ns ns ns ns 3.6 3.3 3.1 3.0 2.8 38.4 9.8 6.9 5.7 4.6 4.2 19.5 11.2 8.8 6.4 5.7 ns ns ns ns ns ns 50 180 300 405 420 480 MHz MHz MHz MHz MHz MHz 3.1 3.1 2.6 2.6 2.4 24.6 7.0 5.0 4.3 3.7 3.5 13.2 6.7 6.5 5.0 4.4 ns ns ns ns ns ns 3.0 2.7 2.3 2.1 2.0 28.1 7.6 5.3 4.4 3.5 3.1 14.8 8.7 6.8 5.0 4.3 ns ns ns ns ns ns Min Typ [1] Max Unit Tamb = 25 C; CL = 15 pF 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 11 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 9: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol fmax Parameter maximum input clock frequency CP Conditions see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 C tW pulse width HIGH or LOW CP see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V pulse width LOW MR see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V trem removal time MR see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tsu(H) set-up time HIGH D to CP see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.5 0.4 0.5 0.3 0.2 ns ns ns ns ns ns -1.1 -2.0 -0.5 -0.9 -1.0 ns ns ns ns ns ns 9.0 3.0 1.75 1.35 0.9 0.8 ns ns ns ns ns ns 5.25 1.6 1.0 0.75 0.6 0.55 ns ns ns ns ns ns 35 130 200 240 275 300 MHz MHz MHz MHz MHz MHz Min Typ [1] Max Unit 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 12 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 9: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol tsu(L) Parameter set-up time LOW D to CP Conditions see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V th hold time D to CP see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CPD power dissipation capacitance f = 1 MHz VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] All typical values are measured at nominal VCC. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC. [2] [3] Min - Typ 0.8 0.6 0.4 0.4 0.5 -0.7 -0.5 -0.5 -0.3 -0.4 1.8 1.9 1.9 2.0 2.3 2.7 [1] Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF pF pF pF [3] 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 13 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 10: Dynamic characteristics GND = 0 V; see Figure 9 Symbol CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum input see Figure 7 clock frequency CP VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q see Figure 7 V CC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.6 2.4 2.2 1.9 1.8 11.7 7.6 6.3 4.7 4.1 2.6 2.4 2.2 1.9 1.8 13.6 7.8 6.3 4.9 4.3 ns ns ns ns ns 2.4 2.0 1.8 1.5 1.3 13.6 8.4 6.6 4.7 4.0 2.4 2.0 1.8 1.5 1.3 13.6 8.7 6.9 5.0 4.2 ns ns ns ns ns 2.2 2.1 1.7 1.5 1.3 170 310 400 490 550 10.0 6.4 5.4 4.0 3.3 2.2 2.1 1.7 1.5 1.3 12.0 6.6 5.6 4.0 3.6 ns ns ns ns ns MHz MHz MHz MHz MHz MHz 2.2 1.8 1.3 1.1 1.0 11.9 7.3 5.9 4.0 3.3 2.2 1.8 1.3 1.1 1.0 12.0 7.6 6.2 4.2 3.5 ns ns ns ns ns Parameter Conditions -40 C to +85 C Min Max -40 C to +125 C Min Max Unit 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 14 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 10: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol fmax Parameter Conditions -40 C to +85 C Min maximum input see Figure 7 clock frequency CP VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum input see Figure 7 clock frequency CP VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.9 2.6 2.5 2.2 2.1 120 190 240 300 320 13.5 8.6 7.2 5.4 4.8 2.9 2.6 2.5 2.2 2.1 15.2 9.1 7.4 5.5 5.0 ns ns ns ns ns MHz MHz MHz MHz MHz MHz 2.8 2.3 2.1 1.9 1.7 15.2 9.4 7.4 5.3 4.7 2.8 2.3 2.1 1.9 1.7 15.4 9.9 7.9 5.6 4.9 ns ns ns ns ns 150 280 310 370 410 Max -40 C to +125 C Min Max MHz MHz MHz MHz MHz MHz Unit 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 15 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 10: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum input see Figure 7 clock frequency CP VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 5 pF, 10 pF, 15 pF, 30 pF tW pulse width HIGH or LOW CP see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V pulse width LOW MR see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V trem removal time MR see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 74AUP1G175_1 Parameter Conditions -40 C to +85 C Min Max -40 C to +125 C Min Max Unit 3.4 3.2 2.9 2.6 2.5 3.7 3.6 3.4 2.9 3.1 70 120 150 190 200 20.6 12.4 9.6 6.9 6.5 18.6 11.6 9.6 7.2 6.4 - 3.4 3.2 2.9 2.6 2.5 3.7 3.6 3.4 2.9 3.1 - 21.0 13.0 10.2 7.3 6.9 19.8 12.2 9.7 7.2 6.9 - ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz MHz 1.5 0.9 0.7 0.4 0.4 4.9 2.5 1.8 1.1 0.8 -1.2 -0.8 -0.7 -0.4 -0.2 - 1.5 0.9 0.7 0.4 0.4 4.9 2.5 1.8 1.1 0.8 -1.2 -0.8 -0.7 -0.4 -0.2 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 16 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Table 10: Dynamic characteristics ...continued GND = 0 V; see Figure 9 Symbol tsu(H) Parameter set-up time HIGH D to CP Conditions see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tsu(L) set-up time LOW D to CP see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V th hold time D to CP see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.2 0 0 0 0 0.2 0 0 0 0 ns ns ns ns ns 1.7 1.1 0.9 0.9 0.9 1.7 1.1 0.9 0.9 0.9 ns ns ns ns ns 1.2 0.8 0.6 0.5 0.5 1.2 0.8 0.6 0.5 0.5 ns ns ns ns ns -40 C to +85 C Min Max -40 C to +125 C Min Max Unit 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 17 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 13. Waveforms VI D input GND th tsu 1/fmax VI CP input GND tW tPHL VOH Q output VOL VM 001aaa465 VM th tsu VM tPLH Measurement points are given in Table 11. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum input clock frequency Table 11: VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 x VCC Input VM 0.5 x VCC VI VCC tr = tf 3.0 ns Supply voltage 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 18 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger VI MR input GND tW VI CP input GND t PHL VOH Q output VOL VM 001aaa464 VM t rem VM Measurement points are given in Table 12. VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width and the MR to CP removal time Table 12: VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 x VCC Input VM 0.5 x VCC VI VCC tr = tf 3.0 ns Supply voltage 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 19 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger VCC VEXT 5 k PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 13. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times Table 13: VCC 0.8 V to 3.6 V [1] Test data Load CL RL [1] Supply voltage VEXT tPLH, tPHL tPZH, tPHZ GND tPZL, tPLZ 2 x VCC 5 pF, 10 pF, 5 k or 1 M open 15 pF and 30 pF For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M. 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 20 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 14. Package outline Plastic surface mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 97-02-28 04-11-08 Fig 10. Package outline SOT363 (SC-88) 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 21 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4x L1 L (2) e 6 e1 5 e1 4 6x (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 11. Package outline SOT886 (XSON6) 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 22 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 L1 e L 6 e1 5 e1 4 A A1 D E terminal 1 index area 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 Fig 12. Package outline SOT891 (XSON6) 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 23 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 15. Abbreviations Table 14: Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor Transistor Logic 16. Revision history Table 15: Revision history Release date 20060327 Data sheet status Preliminary data sheet Change notice Doc. number Supersedes Document ID 74AUP1G175_1 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 24 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 17. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Trademarks Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74AUP1G175_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx -- 27 March 2006 25 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information . . . . . . . . . . . . . . . . . . . . 25 (c) Koninklijke Philips Electronics N.V. 2006 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 27 March 2006 Document number: 74AUP1G175_1 Published in The Netherlands |
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